Set All Bits to 1

To set all bits of a logic signal to 1, you can simply assign -1 to it. This takes advantage of the fact that in 2’s complement representation, -1 results in all bits being set to 1, regardless of the bit width of the logic signal.

For example, given the following logic definitions, assign -1 as shown:

logic(b[8]) <= -1
logic(c[16]) <= -1
logic(d[4][16]) <= -1

The resulting VHDL code will be:

a <= '1';
b <= x"ff";
c <= x"ffff";
d <= (others=>x"ffff");