Active-High and Active-Low

When writing HDL, both active-high and active-low logic are used, but SCode defaults to active-high. Similarly, clock edges default to the rising edge.

The following example increments data on the rising edge of a clock. When the reset signal is high, the data becomes 0.

sequence(clk)
    data <= (0, reset == 1, data + 1)  

sequence(clk)
    data <= (0, reset, data + 1) # Same as the above example; if a logic signal is provided instead of an expression, it is automatically recognized as active-high.

When using And/Or with 1-bit logic, there is the advantage of not having to explicitly use an expression.

o1 <= (i1, And(a == 1, b == 1), i2)
o1 <= (i1, a & b, i2)  # A simpler way to express the same logic as above.

However, signals external to an FPGA chip often use active-low logic. In such cases, it is best to change the polarity either immediately at the input or just before the FPGA output. In other words, adjust the polarity at the top-level module’s I/O to match the external signals, and use active-high logic within all other internal modules.

reset <= ~reset_n  # Convert an active-low input signal into an active-high reset signal using a NOT gate.

out_en_n <= ~out_en # Invert the polarity of an active-high enable signal right before output.