forgen

VHDL uses for generate and for loop statements to express repetitive tasks.

for generate is used in concurrent statements, while for loop is used in sequential statements.

For example, if you have an AND gate component and want to connect 32 of them, you would use for generate:

component and02
    port( 
        a0 : in std_logic;
        a1 : in std_logic;
        y : out std_logic
    );
end component and02;

g1 : for n in 0 to 31 generate
    and_gate : and02 port map( a0 => sig1(n), a1 => sig2(n), y => z(n));
end generate;

The following shows a for loop written inside a process:

process(clk)
begin
    if rising_edge(clk) then 
        for i in 0 to 31 loop 
            out_sig(i) <= in_sig(i);
        end loop;
    end if;
end process;

In SCode, you don’t need to distinguish between generate and loop; simply use a Python for loop. Similarly, it doesn’t matter whether you are writing concurrent or sequential statements. The examples above are written in SCode as follows:

# 1. generate
for n in range(32) : 
    imodule("and02.sc", a0=sig1[n], a1=sig2[n], y=z[n])

# 2. loop
with sequence(clk) : 
    for i in range(32) : 
        out_sig[i] <= in_sig[i]