When using an external reset signal for an FPGA, recovery and removal time violations can occur at the flip-flops (FF), potentially leading to unknown states.
Recovery time corresponds to setup time, while removal time corresponds to hold time.
- Recovery time: The minimum time required between the de-assertion of an asynchronous control signal and the next active clock edge.
- Removal time: The minimum time required between an active clock edge and the de-assertion of an asynchronous control signal.
To prevent violations, a reset synchronizer should be used. The construction of the synchronizer varies depending on whether it is for a synchronous or asynchronous reset.
Synchronous Reset Synchronizer
Asynchronous Reset Synchronizer
For asynchronous resets, the number of flip-flops can be adjusted to control the width of the reset pulse.