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Creating Functions

When you use SCode statements within a function, they are converted into VHDL/Verilog. However, you need to be careful when passing parameters to these functions.

SCode has a feature that automatically converts a logic signal into an active-high expression when an expression is required.

logic(enable)
with sequence(clk):
    count <= (count + 1, enable)

In the code above, the enable logic signal is used where a conditional expression like enable == 1 is expected. When a logic signal is provided instead of an expression in such a context, SCode treats it as active-high and converts it to something equivalent to enable == 1.

However, when this logic is implemented inside a function, the function doesn’t know whether the calling code will pass a logic signal or a full expression as a parameter. To support both, the function should use the provided parameter directly without modifying it.

def test_func(clk, enable):
    count = logic_unique("count")
    with sequence(clk):
        count <= (count + 1, enable) 
    return count

When a function is written this way, the calling side can provide either a logic signal or an expression:

  • count <= test_func(clk, enable): Increments when enable is high.
  • count <= test_func(clk, enable == 0): Increments when enable is low.

If the function were written with enable == 1 inside, the first case would work fine, but the second case would effectively become (enable == 0) == 1, which would cause a syntax error.

In SCode, using logic signals directly is more convenient than full expressions and helps prevent unexpected errors when writing functions.

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