The format for conditional assignments in SCode is as follows:
destination <= (value1, condition1, value2, condition2, value3, ...)
In this structure, value1 is assigned if condition1 is true, value2 is assigned if condition2 is true, and so on. Note that for combinational logic, because there are no registers to hold a previous state, there must always be one more value than there are conditions (to provide a default “else” case).
Unlike standard VHDL or Verilog, SCode allows this same conditional assignment format for both combinational and sequential statements. While sequential statements also support if statements, using conditional assignments as shown is generally recommended for consistency.
This approach is particularly useful when you need to switch logic between being combinational and sequential, as the same assignment format works in both contexts.
In sequential statements, SCode’s conditional assignments support recursion. This means you can nest another conditional assignment where a value would normally go, which is useful for implementing complex nested if structures.
destination <= (value1, condition1, (value2, condition2, value3, ...))
Combinational Statement Example
b <= (1, a, 0)
c <= (d, -a, e)
# Converted code
b <= '1' when a = '1' else '0';
c <= d when a = '0' else e;
Sequential Statement Example
with sequence(clk, srst=reset):
f <= (a, -b)
g <= (1, a, (b, c, d))
# Converted code
process(clk)
begin
if rising_edge(clk) then
if reset = '1' then
f <= '0';
g <= '0';
else
if b = '0' then
f <= a;
end if;
if a = '1' then
g <= '1';
else
if c = '1' then
g <= b;
else
g <= d;
end if;
end if;
end if;
end if;
end process;
As you can see, expressing sequential logic using SCode’s conditional assignments is often much more concise than using traditional if statements.