Zero Filling

In VHDL and Verilog, an error occurs if the source and destination bit widths in an assignment do not match.

SCode, however, automatically fills the upper bits with zeros if the destination width is larger than the source width.

For instance, suppose logic b is 4 bits wide and logic a is 1 bit wide, and you assign a to b:

logic(a)
logic(b[4])

b <= a

SCode performs zero-filling, and the resulting VHDL code looks like this:

b <= "000" & a;

Conversely, if you attempt to assign b (4 bits) to a (1 bit), an error will occur:

a <= b

# Error: Width of destination[1] and source[4] should be same

This error indicates that the 1-bit destination cannot accommodate the 4-bit source.