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Mapping 1D Logic to Arrays

In SCode, 2D ports are implemented as 1D vectors in the generated code. This is because some Verilog versions do not support 2D arrays in ports, and in VHDL, using 2D ports requires the additional complexity of using packages.

For example, even if you declare a 2D outport as outport("data[4][8]") in SCode, it is implemented as a 1D vector.

This approach works fine for indexing and accessing values within SCode, as indices are automatically converted into 1D vector slices. However, it can make it difficult to interpret individual values during simulation.

N = 4
outport("count[N][10]")

for i in range(N):
    count[i] <= i

In the example above, count is declared as 2D multi-logic, but it is converted into 1D logic:

entity mv_sim is
    port (
        count               : out std_logic_vector(39 downto 0)
    );
end entity;

architecture arch_mv_sim of mv_sim is

begin
    count(9 downto 0) <= (others=>'0');
    count(19 downto 10) <= ("00" & x"01");
    count(29 downto 20) <= ("00" & x"02");
    count(39 downto 30) <= ("00" & x"03");

end architecture;

When you write a testbench for this module, such as mv_sim_tb.sc, and run a simulation, the count value might appear as a single long hex string like 0x00c0200400, which is hard to read.

# mv_sim_tb.sc
testbench('mv_sim.sc')

To make the values easier to interpret, you can map the 1D vector back to a 2D array in your testbench:

# mv_sim_tb.sc
testbench('mv_sim.sc')

array("count_arr[%s][%s]" % (len(count), count.width))

for i in range(4):
    count_arr[i] <= count[i]

By declaring the count_arr array and assigning the count output to it, you can easily view individual elements in the simulation.

The converted VHDL code will look like this:

entity mv_sim_tb is
end entity;

architecture arch_mv_sim_tb of mv_sim_tb is
type std_10bit_array is array (natural range <>) of std_logic_vector(9 downto 0);
component mv_sim
    port (
        count               : out std_logic_vector(39 downto 0)
    );
end component;

signal count                : std_logic_vector(39 downto 0);
signal count_arr            : std_10bit_array(3 downto 0);

begin

    u0_mv_sim : mv_sim port map (
        count               => count
    );
    count_arr(0) <= count(9 downto 0);
    count_arr(1) <= count(19 downto 10);
    count_arr(2) <= count(29 downto 20);
    count_arr(3) <= count(39 downto 30);

end architecture;
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