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Handling Unused Sub-module Outputs

When instantiating a sub-module, you may not need all of its output ports. In VHDL, these are connected as open, and in Verilog, they are left as empty connections.

In SCode, you represent unused outputs using the Python built-in constant None.

Suppose a sub-module named test_sub has the following port definitions, and we want to use data but not data2:

# test_sub port information
inport(clk, reset)
outport(data[8])
outport(data2[8])

The SCode to instantiate test_sub would be:

imodule("test_sub.sc",
    clk = clk,        
    reset = reset,        
    data = data,
    data2 = None,
)

Alternatively, if you simply omit data2 from the imodule call entirely, SCode automatically assigns it to None.

The resulting VHDL and Verilog code is as follows:

-- VHDL
u0_test_sub : test_sub port map (
    clk                 => clk,
    reset               => reset,
    data                => data,
    data2               => open
);
// Verilog
test_sub u0_test_sub (
    .clk                (clk),
    .reset              (reset),
    .data               (data),
    .data2              ()
);
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